###############################################################################
# Created by write_sdc
# Sun Jul 28 07:47:22 2024
###############################################################################
current_design dft_top
###############################################################################
# Timing Constraints
###############################################################################
create_clock -name clk -period 1.0000 [get_ports {clk}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X0[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X1[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X2[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[0]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[10]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[11]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[12]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[13]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[14]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[15]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[1]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[2]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[3]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[4]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[5]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[6]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[7]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[8]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {X3[9]}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {next}]
set_input_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {reset}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y0[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y1[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y2[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[0]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[10]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[11]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[12]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[13]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[14]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[15]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[1]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[2]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[3]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[4]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[5]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[6]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[7]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[8]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {Y3[9]}]
set_output_delay 0.2000 -clock [get_clocks {clk}] -add_delay [get_ports {next_out}]
###############################################################################
# Environment
###############################################################################
###############################################################################
# Design Rules
###############################################################################
